1. Field of the Invention
The present invention relates to a technique of forming a copper interconnection on a semiconductor wafer.
2. Description of the Related Art
In manufacturing a semiconductor device such as an IC (Integrated Circuit), an LSI (Large Scale Integrated Circuit) or the like, there are normally taken the steps of forming an insulating film on the surface of a semiconductor wafer such as a silicon wafer or the like, and thereafter forming, thereon, a photoresist patterned into a prescribed shape and carrying out the etching of the insulating film, using the photoresist as a mask. A trench or a hole required for formation of an interconnection, an interlayer via plug or such is formed through the steps of this sort.
Now, the formation of an insulating film and a metal film for an interconnection is performed over the entire surface of the wafer at a time so that these films are formed even in the area close to the wafer edge that is not utilized for chips. If the metal film and the insulating film are left behind in such an area, the peeling-off of the film may take place during the subsequent manufacturing steps, and, consequently, the contamination of the wafer and manufacturing apparatus may be brought about.
Further, the formation of the photoresist is also performed over the entire surface of the wafer, but the exposure for the resist is not applied to the area close to the wafer edge. As a result, in the case that a positive resist is used, the resist remains in the vicinity of the wafer edge even after the development. This remaining resist may cause the peeling-off of the film or the like, while transferring and holding the wafer, which leads to the contamination of the adjacent apparatus and the wafer surface and, consequently, a lowering of the production yield.
To overcome this problem, after the photoresist is formed and patterned into a prescribed shape, the step of removing the photoresist in the vicinity of the wafer edge is carried out. This prevents the contamination by the photoresist that is left in the vicinity of the wafer edge. Moreover, with the resist in the vicinity of the wafer edge being taken away, the insulating film and the like in this area can be removed by etching so that the contamination caused by the peeling-off of the insulating film and the like can be prevented.
When a positive resist is employed, the step of removing the photoresist in the vicinity of the wafer edge is normally carried out by means of peripheral exposure. That is, in addition to the exposure applied to the pattern formation region, the peripheral exposure of the wafer is performed to remove the unnecessary resist lying in the peripheral area. The peripheral exposure of the wafer is made, for example, while rotating the wafer that is coated with a resist so as to achieve the exposure of a ring-shaped neighbouring area of the wafer edge. FIG. 17 is a top plan view of a semiconductor wafer and, by the peripheral exposure, a wafer edge neighbouring area 50 is exposed and then removed by means of dissolution in a later step. Meanwhile, an unexposed area 51 including element formation regions remains, thereat, without being removed by dissolution. Further, the peripheral exposure can be performed along the whole circumference of the wafer or only a part of the wafer edge.
FIG. 18 is a series of schematic cross-sectional views showing the steps of a manufacturing method including the step of peripheral exposure. These steps are described below. Firstly, after a silicon oxynitride film 2 and a silicon oxide film 3 are formed, in this order, over an element formation layer 1 in which an element such as a transistor or the like is formed, a coating of a photoresist material is applied thereto and then dried (FIG. 18(a)). Next, through a mask patterned into a prescribed shape, an element formation region is subjected to exposure, whereby unexposed sections 4a and exposed sections 4b are formed therein (FIG. 18(b)). Subsequently, performing peripheral exposure, the silicon oxide film in the vicinity of the wafer edge (shown on the left side of the drawing) is made an exposed section 4b (FIG. 18(c)). After these exposures are made, the exposed sections 4b are removed by dissolution with a chemical solution. FIG. 19(a) shows the state after this removal is made. Now, using the photoresist 4 as a mask, dry etchings are carried out, whereby the silicon oxide film 3 is first removed and then the silicon oxynitride film 2 is removed. In etching these films, appropriate etching gases are used, respectively. FIG. 19(b) shows the state after the etchings are completed. After that, by ashing and a wet treatment with a resist peeling-off agent, the photoresist 4 is removed (FIG. 19(c)). Through the steps described above, there reaches the state in which the silicon oxide film 3 and the silicon oxynitride film 2 in the vicinity of the wafer edge are removed.
Next, referring to FIGS. 10 to 14, a conventional forming method of copper interconnections including the above steps of peripheral exposure is described below. Firstly, after a silicon oxynitride film 2 and a silicon oxide film 3 are formed, in this order, over an element formation layer 1 in which an element such as a transistor or the like is formed (FIG. 10(a)). In each drawing, there are shown an element formation region 25 and a wafer edge neighbouring region 26. The term a xe2x80x9cwafer edge neighbouring regionxe2x80x9d 26 as used herein denotes a ring-shaped region along the wafer edge where no element formation is made. As against this, an xe2x80x9celement formation regionxe2x80x9d 25 indicates a region that is situated inside of the wafer edge neighbouring region 26 and sectioned into with scribe lines. The wafer edge neighbouring area 50 and an area 51 including element formation regions have the positioning relation, for example, as shown in FIG. 17.
Next, a coating of a photoresist material is applied thereto and then dried. Next, through a mask patterned into a prescribed shape, an element formation region 25 is subjected to exposure, and then peripheral exposure is applied to the wafer edge neighbouring region 26. After these exposures are made, the exposed sections are removed by dissolution with a chemical solution. FIG. 10(b) shows the state after this removal is made. Now, using the photoresist 4 as a mask, dry etchings are carried out, whereby the silicon oxide film 3 is first removed and then the silicon oxynitride film 2 is removed. In etching these films, optimum etching gases are used, respectively. By these etchings , a trench for an interconnection is formed in the element formation region 25 and, at the same time, an insulating film and the like in the wafer edge neighbouring region 26 are removed. FIG. 10(c) shows the state after the etchings are completed. After that, by ashing and a wet treatment with a resist peeling-off agent, the photoresist 4 is removed.
Next, after a Ta (tantalum) film 5 is grown over the entire surface by the sputtering method, a copper film 6 is grown by the electroplating method, the CVD (Chemical Vapour Deposition) method or the like. (FIG. 11(a)). After these films are grown, superfluous portions of the copper film 6 and the Ta film 5 are removed, by polishing, using the CMP (Chemical Mechanical Polishing) so as to form a damascene interconnection (buried-type interconnection). In the vicinity of the wafer edge (the left end in the drawing), hereat, some of the copper film 6 and the Ta film 5 are left behind in a stepped part and polishing remains are generated (FIG. 11(b)).
Next, after a silicon oxynitride film 7 is grown over the entire surface of the wafer by the plasma CVD method or the like, a silicon oxide film 8 is grown by the plasma CVD method (FIG. 12(a)). Next, after a coating of a photoresist material is applied thereto and then dried, the exposure for patterning of the element formation region as well as the peripheral exposure are performed in the same way as the step shown in FIG. 10 (b). This forms a photoresist 9 into a shape, wherein openings are made in a prescribed position of the element formation region as well as over the wafer edge neighbouring area (FIG. 12(b)).
Using this photoresist 9 as a mask, dry etchings are carried out, whereby the silicon oxide film 8 is first removed and then the silicon oxynitride film 7 is removed (FIG. 12(c)). In etching these films, appropriate etching gases are used, respectively.
Next, after a Ti/TiN layered film 10 is grown over the entire surface by the sputtering method, a tungsten film 11 is grown by the electroplating method, the CVD method or the like. (FIG. 13(a)). After these films are grown, superfluous portions of the tungsten film 11 and the Ti/TiN layered film 10 are removed, by polishing, using the CMP so as to form an interlayer via plug. In the vicinity of the wafer edge, hereat, some of the tungsten film 11 and the Ti/TiN layered film 10 are left behind on the second step of a stepped part and polishing remains are generated. These polishing remains hardly bring about a problem of contamination or the like so that they are omitted from the drawings.
After that, in the same way as the steps described above, a silicon oxynitride film 12 and a silicon oxide film 14 are grown (FIG. 13(b)) and, over these films, a photoresist 20 is formed into a shape, wherein openings are made in a prescribed position of the element formation region as well as over the wafer edge neighbouring area (FIG. 13(c)). After that, using this photoresist 20 as a mask, dry etching is performed and thereby a recess section is formed in the element formation region and, at the same time, a silicon oxide film 14 and the like in the wafer edge neighbouring region are removed. Next, through the same steps a shown in FIG. 11(a) and (b), a copper interconnection is formed on the interlayer via plug that is made of a tungsten film 11 and a Ti/TiN layered film 10 (FIG. 13(d)).
When multi-layered interconnections are formed by the steps described above, however, there is left a layered body 23 of polishing remains with Ta films and copper films lying alternately in the vicinity of the wafer edge as shown in an encircled part of FIG. 13(d). Since the adhesion between copper and Ta is particularly weak, the peeling-off of the film takes place in the layered portion described above, and contamination of the wafer and apparatus may be brought about. Further, while a Ta film is formed as a barrier metal to cover lateral and bottom faces of a copper film in the steps described above, even when a film containing another material, for example, a titanium-containing film is employed, the adhesion between copper and barrier metal is similarly poor and causes contamination.
An example of formation of multi-layered interconnections, using a so-called single damascene process is described so far, but a similar problem arises when a dual damascene process is employed. FIG. 14 illustrates an example of a conventional method of forming multi-layered interconnections using a dual damascene process. Firstly, after a silicon oxynitride film 2 and a silicon oxide film 3 are formed over an element formation layer 1 in which an element (not shown in the drawing) such as a transistor or the like is formed, a copper interconnection comprising a Ta film 5 and a copper film 6 is formed (FIG. 14(a)). using the damascene process described above (FIG. 11). Polishing remains 21 is, hereat, generated in the wafer edge neighbouring area. Next, through etching, a sectionally T-shaped through hole is formed in the element formation region 25, and at the same time, a silicon oxide film 8 in the wafer edge neighbouring area is removed (FIG. 14(b)). After that, by carrying out the film growth and the CMP, a copper interconnection comprising a Ta film 18 and a copper film 19 is formed (FIG. 14(c)). In this case, too, a layered body 23 of polishing remains is generated in the wafer edge neighbouring area, causing a problem of contamination of the wafer and apparatus due to the peeling-off of the film.
The above problem does not arise when aluminum interconnections or copper-aluminum interconnections are employed. With aluminum interconnections or such, the peeling-off of the film hardly occurs even if etching residues of these films are generated in the vicinity of the wafer edge, owing to the good adhesion between the interconnection material and barrier metal. Referring to cross-sectional views of FIG. 16, this point is described further below.
FIG. 16(a) is a view showing the state at which a copper-aluminum interconnection (a lower-layer interconnection) comprising a Ti-based film 32, a copper-aluminum film 33 and a Ti-based film 34 is formed and thereafter, over that, an interlayer insulating film 36 is grown and then a through hole is formed. Following this, a Ti/TiN layered film 38 and a tungsten film 39 are grown (FIG. 16(b)), and then a copper-aluminum interconnection (an upper-layer interconnection) comprising a Ti-based film 32, a copper-aluminum film 33 and a Ti-based film 34 is formed (FIG. 16(c)). Although etching residues of the lower-layer interconnection and the upper-layer interconnection are, hereat, generated in a stepped part in the vicinity of the wafer edge (the left side of the drawings), these etching residues hardly cause the peeling-off of the film or bring about a problem of contamination or the like, because of the good adhesion between the copper-aluminum film and the Ti-based film.
The afore-mentioned problem of the contamination caused by the peeling-off of the film within de posit left in the vicinity of the wafer edge has not, hitherto, drawn much attention, and consequently the measures against this problem have been hardly taken. However, as the semiconductor device achieves a further miniaturization and attains a better performance capability, measures against such a problem have gained in importance. Further, in recent years, demands for a multi-layered interconnection structure have risen considerably. Yet, there remains the problem of the peeling-off of the film that becomes even more pronounced when two or more layers and particularly three or more layers of copper interconnections constitute a multi-layered interconnection structure, since a layered body of polishing remains becomes also multi-layered in such a case.
An object of the present invention is to solve a problem specific to such a forming method of a copper interconnection. Accordingly, an object of the present invention is to prevent deposition of a copper film and a barrier metal in the vicinity of the wafer edge, in forming a copper interconnection, and particularly in forming multi-layered interconnection with a structure wherein multi-layers of copper interconnections are laid, and thereby prevent contamination of the wafer and apparatus which may be caused by the peeling-off of the film.
In light of the above problems, the present invention provides a method of forming a copper interconnection; which comprises the steps of
(a) forming a first insulating film on the entire surface of a semiconductor wafer, and thereafter, together with forming a trench within the first insulating film by etching, removing a portion of the first insulating film along the circumference end part of the semiconductor wafer so as to make the circumference end part of the first insulating film recede inside of the circumference end part of the wafer;
(b) forming a barrier metal film and a copper film, in this order, over the entire surface of the semiconductor wafer and thereafter polishing these films by means of chemical mechanical polishing, and thereby forming a copper interconnection in said trench; and
(c) forming a second insulating film on the entire surface of the semiconductor wafer, and thereafter,. removing a portion of the second insulating film along the circumference end part of the semiconductor wafer so as to make the circumference end part of the second insulating film recede inside of the circumference end part of the wafer; wherein:
the circumference end part of the second insulating film after the completion of step (c) is made to be placed in an outer position than the circumference end part of the first insulating film after the completion of step (a).
This forming method of a copper interconnection makes the circumference end part of the second insulating film after the completion of step (c) placed in an outer position than the circumference end part of the first insulating film after the completion of step (a). This allows of providing a structure in which the polishing remains of a barrier metal film and the copper film that are generated in the vicinity of the wafer edge in performing step (b) are covered with the second insulating film. As a result, contamination caused by the peeling-off of the film that may occur within these polishing remains can be prevented with effect. In the above method of forming a copper interconnection, the circumference end part of each insulating film is made to recede inside of the circumference end part of the wafer in step (a) and (c). These steps can be carried out, for example, by removing a portion of the photoresist in the vicinity of the wafer edge by peripheral exposure or the like so as to form an opening, and thereafter applying etching over the insulating film. In such a method, in order to make the circumference end part of the second insulating film after the completion of step (c) placed in an outer position than the circumference end part of the first insulating film after the completion of step (a), the width of the opening of the photoresist in the vicinity of the wafer edge formed by removing the second insulating film should be made smaller than the width of the opening of the photoresist in the vicinity of the wafer edge formed by removing the first insulating film. Meanwhile, within the second insulating film, a via plug to connect with a copper interconnection can be set appropriately.
In the above method of forming a copper interconnection, if steps (a) to (c) are repeated twice or more times, the effect of the present invention becomes more significant. As the semiconductor device achieves a further miniaturization and attains a better performance capability, demands for a multi-layered interconnection structure have risen considerably, in recent years. However, as described in the section Prior Art, to form a multi-layered interconnection, there has been, hitherto, a problem that a layered body 23 of polishing remains is generated in the wafer edge neighbouring area as shown in FIG. 13(d). In contrast with this, the present invention makes the circumference end part of the second insulating film after the completion of step (c) placed in an outer position than the circumference end part of the first insulating film after the completion of step (a) so that a structure in which polishing remains generated in forming a lowerlayer copper interconnection and polishing remains in forming an upper-layer copper interconnection are separated by an insulating film can be attained. Therefore, generation of the layered body of the polishing remains can be prevented. The problem of the peeling-off of the film becomes very pronounced when two or more layers and particularly three or more layers of polishing remains form a multi-layered body. Consequently, when the present invention is applied to the formation of a multi-layered interconnection structure for which steps (a) to (c) are required to be repeated twice or more times and particularly thrice or more times, the effect of the present invention becomes more significant. Further, when the steps (a) to (c) are repeated twice or more, as described above, if the circumference end part of the second insulating film after the completion of step (c) is made to be placed in an outer position than the circumference end part of the first insulating film after the completion of step (a) that is performed immediately after said step (c), the area of the element formation region can be made larger in the result, which is preferable in view of the layout efficiency of the wafer.
Further, the present invention provides a semiconductor wafer, which comprises:
a first insulating film in which a copper interconnection is set; and
a second insulating film in which a via plug to connect with said copper interconnection is set, with a first insulating film and a second insulating film being laid in alternate order on the main surface of the wafer; wherein:
said copper interconnection comprises a copper film and a barrier metal film wrapping the lateral and bottom faces of said copper film; and
the circumference end part of the second insulating film is placed in an outer position than the circumference end part of the first insulating film.
In this semiconductor wafer, the circumference end part of the second insulating film is placed in an outer position than the circumference end part of the first insulating film. This allows of providing a structure in which the polishing remains that are generated in forming a copper interconnection are covered with the second insulating film and, therefore, contamination caused by the peeling-off of the film that may occur within these polishing remains can be prevented with effect.
Further, in the semiconductor wafer, if two or more layers and particularly three or more layers of the firs insulating films and the second insulating films each are laid in alternate order, the effect of the present invention becomes more significant. This results from the fact that, in this way, there can be attained a structure in which polishing remains generated in forming a lower-layer copper interconnection and polishing remains generated in forming an upper-layer copper interconnection are separated by an insulating film so that a layered body of the polishing is hardly generated. Moreover, herein, in a structure wherein two or more layers of the first insulating films and the second insulating films each are laid, if it is arranged that the circumference end part of the second insulating film is placed in an outer position than the circumference end part of the first insulating film that is formed immediately above the second insulating film, the area of the element formation region can be made larger in the result, which is preferable in view of the layout efficiency of the wafer.
In the present invention, the barrier metal film is preferably i) a film containing tantalum, for example, a tantalum film, a tantalum nitride film or a layered film of these films; or ii) a film containing titanium, for example, a titanium film, a titanium nitride film, or a layered film of these films. When a tantalum-containing film or a titanium-containing film is utilized as a barrier metal film of the copper interconnection, although it functions as an excellent barrier, it has, hitherto, a problem such that the peeling-off of the film becomes liable to happen if polishing remains are generated in the vicinity of the wafer edge owing to its poor adhesion with the copper film. Since the present invention can effectively overcome a problem of peeling-off of the film, the above film containing either tantalum or titanium that has excellent characteristics can be utilized without causing a problem in the manufacturing process.
In a forming method of an interconnection according to the present invention, a distance between the circumference end part of the second insulating film after the completion of step (c) and the circumference end part of the first insulating film after the completion of step (a) is preferably not less than 1 mm.
Further, in a semiconductor wafer according to the present invention, a distance between the circumference end part of the second insulating film and the circumference end part of the first insulating film that is formed immediately below said second insulating film is preferably not less than 1 mm. In this manner, the polishing remains present in the vicinity of the wafer edge can be covered satisfactorily with an insulating film so that the problem of peeling-off of the film can be prevented more effectively. Further, the upper limit is not specifically set, but 5 mm or so is more than enough to solve the problem of peeling-off of the film. In this way, the reduction of the layout efficiency of the wafer can be restrained.